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1 click ADD to your Google HomepageLithography shrinks - % Line edge roughness is getting hairy edge
One of the main challenges today in advanced deep submicron (say 45nm) litho is not merely minimum feature size, but acheiving tight linewidth distributions.
If you take a peek at the Intel picture at their site - small SEM pic of their 45nm SRAM memory cell at the Intel site, as a process engineer you can see that MOS IC scaling is getting considerably more challenging than one might otherwise predict, because the line edge roughness is proportionately larger than ANYTHING I have ever seen before in production.
( ed. the pic itself was removed from my site - but the link is good )
The implications of large % linewidth edge roughness, is difficult decreasing % parametric distribution contol (statistics with HUGE sigmas) and this keeps designers up at night to vainly try pushing speed bin yields. This underlying issue is likely why Justin Rattner (Intel CTO) was pleading for new CAD tools to cope with design tolerancing (when the parametric distributions due to % line edge roughness are growing as the process shrinks relentlessly)
My take as a process engineer is that something has to be done to improve the litho pattern transfer, and I suspect it might be EUV, unless this pic of the ram cell is already patterned with EUV litho?
CONT'D - click READ MORE.... for the full scoop.
Or possibly the dry etch nanoscale uniformity / roughness, which at this nm level can be either the dry etch OR the nano-scale morphology of the gate electrode thin films. All in all, fascinating process detective work opportinuties. I'd love to fix this and to hell with the CAD solution. It is root cause a process issue.
MY guess this is keeping many folks up at nite to figure out some more pragmatic solution for 45nm production with tight parametric control needed for predictable circuit design performance.
POSTSCRIPT Feb 15th 2006 - the other interesting aspect to this, is that the image posted by Intel of the 45nm SRAM cell, is a SEM [Scanning Electron Microscope] image. Despite the hullabaloo about AFM metrology, when SEM electron microscope instrumentation is up to snuff, and well designed, no AFM can come close to the speed, accuracy and calibration stability comparable to that acheivable with the best electron optics imaging. It is quite telling that Dr. Mike Kirk, formerly a senior scientist at Park Scientific, is nowVP of the high end imaging & metrology business line at KLA-Tencor, per a recent EE Times news release about the latest SEM metrology tool being fielded at the firm.
wendman
nano nanotech nanotechnology DUV wafer+stepper
silicon deep+submicron 90nm 65nm 45nm 90+nm 65+nm 45+nm
photolithography immersion+photolithography
If you take a peek at the Intel picture at their site - small SEM pic of their 45nm SRAM memory cell at the Intel site, as a process engineer you can see that MOS IC scaling is getting considerably more challenging than one might otherwise predict, because the line edge roughness is proportionately larger than ANYTHING I have ever seen before in production.
( ed. the pic itself was removed from my site - but the link is good )
The implications of large % linewidth edge roughness, is difficult decreasing % parametric distribution contol (statistics with HUGE sigmas) and this keeps designers up at night to vainly try pushing speed bin yields. This underlying issue is likely why Justin Rattner (Intel CTO) was pleading for new CAD tools to cope with design tolerancing (when the parametric distributions due to % line edge roughness are growing as the process shrinks relentlessly)
My take as a process engineer is that something has to be done to improve the litho pattern transfer, and I suspect it might be EUV, unless this pic of the ram cell is already patterned with EUV litho?
CONT'D - click READ MORE.... for the full scoop.
Or possibly the dry etch nanoscale uniformity / roughness, which at this nm level can be either the dry etch OR the nano-scale morphology of the gate electrode thin films. All in all, fascinating process detective work opportinuties. I'd love to fix this and to hell with the CAD solution. It is root cause a process issue.
MY guess this is keeping many folks up at nite to figure out some more pragmatic solution for 45nm production with tight parametric control needed for predictable circuit design performance.
POSTSCRIPT Feb 15th 2006 - the other interesting aspect to this, is that the image posted by Intel of the 45nm SRAM cell, is a SEM [Scanning Electron Microscope] image. Despite the hullabaloo about AFM metrology, when SEM electron microscope instrumentation is up to snuff, and well designed, no AFM can come close to the speed, accuracy and calibration stability comparable to that acheivable with the best electron optics imaging. It is quite telling that Dr. Mike Kirk, formerly a senior scientist at Park Scientific, is nowVP of the high end imaging & metrology business line at KLA-Tencor, per a recent EE Times news release about the latest SEM metrology tool being fielded at the firm.
wendman
nano nanotech nanotechnology DUV wafer+stepper
silicon deep+submicron 90nm 65nm 45nm 90+nm 65+nm 45+nm
photolithography immersion+photolithography
posted by Mark Wendman at 2:29 PM
4 Comments:
SEM is faster, but it still cannot measure LER for Middle or Bottom CD.
Right except there is the electronically tilting beam SEM imaging technology for 3d surface reconstruction.
Do you know the status of that technology?
It was prototyped for demo in the UK about 6 years ago? My understanding is that one of the SEM metrology firms has actually fielded a commercial grade unit with decent throughput and capable of LER measurements?
The curious aspect is that LER does not seem to be getting better in absolute terms? ( which makes it proportionaltely worse with every process shrink optically)
I am curious what avenues have been tried to improve this, what aspect is not resist related, and what aspect is resist / imaging related....
This is actually pretty fascinating as it is a serious limitation to improving CPU and Memory speeds to near theoretical in a given process technology due to random MTT (mean to target CD / linewidth variations) outside of ideal design characteristics in a given "theoretical" process technology / capability.
Good point about LER, it seems to be related to the photoresist.
Some of the effect is due to resist, but I would think it premature to conclude it it solely the resist.
One area barely looked at is shot noise in the exposure illumination. At this scale I would not rule it out.
I also think that how the resist is prepared and processed may be a contributor.
And lastly there are contributions to final structure line edge roughness that are related to the thin film and the etch process / chemistry.
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